The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including, for example, an analog-to-digital conversion circuit including a comparator.
Successive approximation AD (Analog-to-Digital) converters include two types, i.e., a synchronous operation type and an asynchronous operation type. Synchronous operation type successive approximation AD converters, which perform a successive approximation operation in synchronization with an external clock signal, require a high-frequency external clock signal to operate at a high speed. On the other hand, asynchronous operation type successive approximation AD converters internally generate a clock signal based on an externally-input clock signal, thereby making it possible to operate at a higher speed than in the case of using the external clock signal. For this reason, the asynchronous operation type successive approximation AD converters are used for high-accuracy and high-speed AD conversion. The asynchronous operation type successive approximation AD converters can be applied to, for example, wireless communication devices and industrial equipment.
In a successive approximation AD converter called a charge-sharing type successive approximation AD converter, the accuracy of the AD conversion deteriorates due to an offset of a comparator. Accordingly, it is necessary to perform not only the successive approximation operation, but also an offset correction operation to correct the comparator offset to zero. However, it is difficult for applications requiring constant operation, such as wireless communications (WCDMA®, FD-LTE, etc.) and rotary encoders intended for industrial equipment, to perform the correction operation for correcting the comparator offset. It is also possible to employ a method for correcting the comparator offset only once before use (for example, foreground operation). However, the comparator offset varies when there is a change in the environment during use, which leads to deterioration in the accuracy of AD conversion.
In this regard, Japanese Unexamined Patent Application Publication No. 2007-259224 discloses a technique for correcting an offset of a comparator to zero by a background operation. In an AD converter disclosed in Japanese Unexamined Patent Application Publication No. 2007-259224, a comparator input is short-circuited during sampling and a comparator output is held in a capacitor, to thereby correct the offset of the comparator.